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ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 1 ? 2011 xilinx, inc. xilinx, the xilinx logo, virtex, kintex, artix, zynq, spartan, ise, and other designated brands included he rein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. kintex-7 fpga electrical characteristics kintex-7 fpgas are available in -3, -2, -1, and -1l speed grades, with -3 having the highest performance. kintex-7 fpga dc and ac characteristics are specified in commercial, extended, and industrial temperature ranges. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). however, only selected speed grades and/or devices are available in the extended or industrial temperature range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. this kintex-7 fpga data sheet, part of an overall set of documentation on the 7 series fpgas, is available on the xilinx website at www.xilinx.com/7 . all specifications are subject to change without notice. kintex-7 fpga dc characteristics kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 advance product specification ta bl e 1 : absolute maximum ratings (1) symbol description units v ccint internal supply voltage re lative to gnd ?0.5 to 1.1 v for -1l devices: internal supply voltage relative to gnd ?0.5 to 1.0 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 2.0 v v ccaux_io auxiliary supply voltage relative to gnd ?0.5 to 2.06 v v cco output drivers supply voltage relative to gnd for 3.3v hr banks ?0.5 to 3.6 v output drivers supply voltage relative to gnd for 1.8v hp banks ?0.5 to 2.0 v v ccbram supply voltage for the block ram memories ?0.5 to 1.1 v v ccadc xadc supply relative to gndadc ?0.5 to 2.0 v v ccbatt key memory battery backup supply ?0.5 to 2.0 v v ref input reference voltage ?0.5 to 2.0 v v refp xadc reference input relative to gndadc ?0.5 to 2.0 v v in (2) 3.3v or below i/o input voltage relative to gnd (3) (user and dedicated i/os) ?0.5 to v cco +0.5 v 1.8v or below i/o input voltage relative to gnd (3) (user and dedicated i/os) ?0.5 to v cco +0.5 v v ts voltage applied to 3-state 1.8v or below output (3) (user and dedicated i/os) ?0.5 to v cco +0.5 v t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (4) +220 c t j maximum junction temperature (4) +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. the 3.3v and 1.8v i/o absolute maximum limit applied to dc and ac signals. 3. for i/o operation, refer to ug471 : 7 series fpgas selectio resources user guide . 4. for soldering guidelines and thermal considerations, see ug475 : 7 series fpga packaging and pinout specification .
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 2 ta bl e 2 : recommended operating conditions (1) symbol description min max units v ccint internal supply voltage relative to gnd, t j = 0c to +85c 0.97 1.03 v for -1l devices: internal supply voltage relative to gnd, t j = 0c to +85c 0.87 0.93 v v ccaux auxiliary supply voltage relative to gnd, t j = 0c to +85c 1.71 1.89 v v ccaux_io auxiliary supply voltage when set to 1.8v relative to gnd 1.71 1.89 v auxiliary supply voltage when set to 2.0v relative to gnd 1.94 2.06 v v cco (2)(4)(5) supply voltage for 3.3v hr i/o banks relative to gnd, t j = 0c to +85c 1.11 3.45 v supply voltage for 1.8v hp i/o banks relative to gnd, t j = 0c to +85c 1.11 1.89 v v ccbram block ram supply voltage 0.97 1.03 v v ccbatt (3) battery voltage relative to gnd, t j = 0c to +85c 1.0 1.98 v v in i/o input voltage relative to gnd, t j = 0c to +85c gnd ? 0.20 v cco +0.2 v i in (6) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ?10ma notes: 1. all voltages are relative to ground. 2. configuration data is retained even if v cco drops to 0v. 3. v ccbatt is required only when using bitstream encryption. if battery is not used, connect v ccbatt to either ground or v ccaux . 4. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. 5. the configuration supply voltage v cc_config is also known as v cco_0 . 6. a total of 100 ma per bank should not be exceeded. ta bl e 3 : dc characteristics over recommended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost) v v dri data retention v ccaux voltage (below which configuration data might be lost) v i ref v ref leakage current per pin a i l input or output leakage current per pin (sample-tested) a c in (2) die input capacitance at the pad pf i rpu pad pull-up (when selected) @ v in =0v, v cco =3.3v a pad pull-up (when selected) @ v in =0v, v cco =2.5v a pad pull-up (when selected) @ v in =0v, v cco =1.8v a pad pull-up (when selected) @ v in =0v, v cco =1.5v a pad pull-up (when selected) @ v in =0v, v cco =1.2v a i rpd pad pull-down (when selected) @ v in =3.3v a pad pull-down (when selected) @ v in =1.8v a i batt (3) battery supply current na n temperature diode ideality factor n r series resistance ? notes: 1. typical values are specified at nominal voltage, 25c. 2. this measurement represents the die capacitance at the pad, not including the package. 3. maximum value specified for worst case process at 25c.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 3 important note typical values for quiescent supply current are specified at nominal voltage, 85c junction temperatures (t j ). xilinx recommends analyzing static power consumption at t j = 85c because the majority of designs operate near the high end of the commercial temperature range. quiescent supply current is specified by speed grade for kintex-7 devices. use the xpower? estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to calculate static power consumption for conditions other than those specified in ta bl e 4 . ta bl e 4 : typical quiescent supply current symbol description device speed and temperature grade units -3 -2 -1 -1l i ccintq quiescent v ccint supply current xc7k70t ma xc7k160t ma xc7k325t ma xc7k355t ma xc7k410t ma xc7k420t ma xc7k480t ma i ccoq quiescent v cco supply current xc7k70t ma xc7k160t ma xc7k325t ma xc7k355t ma xc7k410t ma xc7k420t ma xc7k480t ma i ccauxq quiescent v ccaux supply current xc7k70t ma xc7k160t ma xc7k325t ma xc7k355t ma xc7k410t ma xc7k420t ma xc7k480t ma i ccaux_io quiescent v ccaux_io supply current xc7k70t ma xc7k160t ma xc7k325t ma xc7k355t ma xc7k410t ma xc7k420t ma xc7k480t ma i ccbram quiescent v ccbram supply current xc7k70t ma xc7k160t ma xc7k325t ma xc7k355t ma xc7k410t ma xc7k420t ma xc7k480t ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (t j ). 2. typical values are for blank configured devices with no output current loads, no acti ve input pull-up resi stors, all i/o pins are 3-state and floating. 3. if dci or differential signaling is used, more accurate quie scent current estimates can be obt ained by using the xpower estim ator (xpe) or xpower analyzer (xpa) tools.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 4 power-on/off power supply requirements xilinx fpgas require a certain amount of su pply current during power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. the recommended power-on and reverse power-off sequence for kintex-7 devices is v ccint , v ccbram , v ccaux , v ccaux_io , and v cco to achieve minimum current draw and ensure i/os are 3-stated at power-up. in cases where the recommended sequence cannot be met, the following rules ensure that the i/os remain 3-stated and no de vice damage will occur. v ccint and v ccbram can be powered on or off at any time as long as the following rules are met: ?v ccaux and v ccaux_io must be powered prior to v cco or v ccaux , v ccaux_io , and v cco can ramp simultaneously if powered by the same supply. ?v ccaux and v cco can be powered by the same supply. ? during operation, the v ccaux ,v ccaux_io , and v ccint voltages must stay within their specifications (see ta b l e 2 ). when powering down, the reverse power-up sequencing rules are recommended for the same reasons given during power up. v cco must be powered down prior to v ccaux and v ccaux_io , or if powered by the same supply, v cco can be powered down simultaneously. in -3, -2, and -1 devices, if v ccint and v ccbram have the same recommended voltage levels, then both can be powered by the same supply. both v ccint and v ccbram can be powered up or down any time during the recommended sequence. ta bl e 5 shows the minimum current, in addition to i ccq , that are required by kintex-7 devices for proper power-on and configuration. if the current minimums shown in ta bl e 4 and ta bl e 5 are met, the device powers on after all three supplies have passed through their power-on reset threshold voltages. the fpga must not be configured until after v ccint is applied. once initialized and configured, use the xpower tools to estimate current drain on these supplies. ta bl e 5 : power-on current for kintex-7 devices device i ccintmin i ccauxmin i ccomin i ccaux_io i ccbram units typ (1) typ (1) typ (1) typ (1) typ (1) xc7k70t ma xc7k160t ma xc7k325t ma xc7k355t ma xc7k410t ma xc7k420t ma xc7k480t ma notes: 1. typical values are specified at nominal voltage, 25c. 2. use the xpower? estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to calculate maximum power-on currents. ta bl e 6 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage relative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage relative to gnd 0.20 to 50.0 ms v ccbram block ram supply voltage relative to gnd 0.20 to 50.0 ms
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 5 selectio? dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 7 : selectio dc input and output levels (1)(2) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl ?0.3 0.8 2.0 3.45 0.4 2.4 note 3 note 3 lvcmos33 ?0.3 0.8 2.0 3.45 0.4 v cco ? 0.4 note 4 note 4 lvcmos25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ? 0.4 note 4 note 4 lvcmos18, lvdci18 ?0.3 35% v cco 65% v cco v cco + 0.3 0.45 v cco ? 0.45 note 5 note 5 lvcmos15, lvdci15 ?0.3 30% v cco 70% v cco v cco + 0.3 25% v cco 75% v cco note 6 note 6 lvcmos12 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note 7 note 7 pci33_3 ?0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco 1.5 ?0.5 hstl i_12 ?0.3 v ref ?0.1 v ref +0.1 v cco + 0.3 25% v cco 75% v cco 6.3 6.3 hstl i (8) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (8) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 16 ?16 diff hstl i (8) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? diff hstl ii (8) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? sstl135 ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 diff sstl135 ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 sstl18 i ?0.3 v ref ? 0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt +0.47 8 ?8 sstl18 ii ?0.3 v ref ? 0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 i ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 v tt ?0.608 v tt + 0.608 ? ? diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? sstl15 ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 v tt ?0.175 v tt + 0.175 17.8 17.8 notes: 1. tested according to relevant specifications. 2. 3.3v and 2.5v standards are only supported in 3.3v i/o banks. 3. supported drive strengths of 4, 8, 12, 16, or 24 ma 4. supported drive strengths of 4, 8, 12, or 16 ma 5. supported drive strengths of 2, 4, 6, 8, 12, or 16 ma in hp i/o banks and 4, 8, 12, 16, or 24 ma in hr i/o banks. 6. supported drive strengths of 2, 4, 6, 8, 12, or 16 ma in hp i/o banks and 4, 8, 12, or 16 ma in hr i/o banks. 7. supported drive strengths of 2, 4, 6, or 8 ma in hp i/o banks and 4, 8, or 12 ma in hr i/o banks. 8. applies to both 1.5v and 1.8v hstl. 9. for detailed interface specific dc voltage levels, see ug471 : 7 series fpgas selectio resources user guide .
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 6 lvds dc specifications (lvds_25) lvds dc specifications (lvds) efuse read endurance and programming conditions ta bl e 1 0 lists the maximum number of read cycle operations expected. ta bl e 1 1 lists the programming conditions specifically for efuse. fo r more information, see ug470 : 7 series fpga configuration user guide . ta bl e 8 : lvds_25 dc specifications symbol dc parameter conditions min typ max units v cco supply voltage v v oh output high voltage for q and q r t = 100 ? across q and q signals v v ol output low voltage for q and q r t = 100 ? across q and q signals v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 ? across q and q signals mv v ocm output common-mode voltage r t = 100 ? across q and q signals v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high mv v icm input common-mode voltage v ta bl e 9 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage v v oh output high voltage for q and q r t = 100 ? across q and q signals v v ol output low voltage for q and q r t = 100 ? across q and q signals v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 ? across q and q signals mv v ocm output common-mode voltage r t = 100 ? across q and q signals v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high common-mode input voltage = 1.25v mv v icm input common-mode voltage differential input voltage = 350 mv v ta bl e 1 0 : efuse read endurance symbol description speed grade units -3 -2 -1 -1l dna_cycles number of dna_port read operations or jtag isc_dna read command operations. unaffected by shift operations. read cycles aes_cycles number of jtag fuse_key or fuse_cntl read command operations. unaffected by shift operations. read cycles ta bl e 1 1 : efuse programming conditions symbol description min typ max units i fs v ccaux supply current ? ? 40 ma t j temperature range 15 ? 85 c
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 7 gtx transceiver specifications gtx transceiver dc characteristics gtx transceiver dc input and output levels ta bl e 1 3 summarizes the dc output specifications of th e gtx transceivers in kintex-7 fpgas. consult ug476 : 7series fpgas gtx transceiver user guide for further details. ta bl e 1 2 : recommended operating conditions for gtx transceivers (1)(2) symbol description min typ max units mgtavcc analog supply voltage for the gtx transmitter and receiver circuits relative to gnd 0.97 1.0 1.03 v mgtavtt analog supply voltage for the gtx transmitter and receiver termination circuits relative to gnd 1.17 1.2 1.23 v mgtavttrcal analog supply voltage for the resistor calibration circuit of the gtx transceiver column 1.17 1.2 1.23 v mgtvccaux auxiliary analog quad pll (qpll) voltage supply for the transceivers 1.75 1.80 1.85 v notes: 1. each voltage listed requires the filter circuit described in ug476 : 7 series fpgas gtx transceiver user guide . 2. voltages are specified for the temperature range of t j = 0c to +85c. ta bl e 1 3 : gtx transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled ? 2000 mv v in absolute input voltage dc coupled mgtavtt = 1.2v ?400 ? mgtavtt mv v cmin common mode input voltage dc coupled mgtavtt = 1.2v ? 2/3 mgtavtt ? mv dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting ? ? 1000 mv v cmoutdc dc common mode output voltage. equation based mgtavtt ? dv ppout /4 mv r in differential input resistance 100 ? r out differential output resistance 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? 10 ps c ext recommended external ac coupling capacitor (2) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in ug476 : 7 series fpgas gtx transceiver user guide and can result in values lower than reported in this table. 2. other values can be used as appropriate to conform to specific protocols and standards.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 8 ta bl e 1 4 summarizes the dc specifications of the clock input of the gtx transceiver. consult ug476 : 7 series fpgas gtx transceiver user guide for further details. x-ref target - figure 1 figure 1: single-ended peak-to-peak voltage x-ref target - figure 2 figure 2: differential peak-to-peak voltage ta bl e 1 4 : gtx transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 2000 mv r in differential input resistance 100 ? c ext required external ac coupling capacitor ? 100 ? nf 0 +v p n d s 1 8 2_01_021611 s ingle-ended volt a ge 0 +v ?v p?n d s 1 8 2_02_021611 differenti a l volt a ge
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 9 gtx transceiver switching characteristics consult ug476 : 7 series fpgas gtx transceiver user guide for further information. ta bl e 1 5 : gtx transceiver performance symbol description output divider speed grade units -3 -2 -1 -1l (1) package type ff sb, fb ff sb, fb ff sb, fb ff sb, fb f gtxmax (2) maximum gtx transceiver data rate 12.5 6.6 10.3125 6.6 6.6 6.6 6.6 6.6 gb/s f gtxmin (2) minimum gtx transceiver data rate 0.500 0. 500 0.500 0.500 0.500 0.500 0.500 0.500 gb/s f gtxcrange cpll line rate range 1 3.2?6.6 gb/s 2 1.6?3.3 gb/s 4 0.8?1.65 gb/s 8 0.5?0.825 gb/s 16 n/a gb/s f gtxqrange1 qpll line rate range 1 1 5.93? 8.0 5.93? 6.6 5.93? 8.0 5.93? 6.6 5.93?6.6 5.93?6.6 gb/s 2 2.965?4.0 2.965?4.0 2. 965?3.3 2.965?3.3 gb/s 4 1.4825?2.0 1.4825?2.0 1.4825?1.65 1.4825?1.65 gb/s 8 0.74125?1.0 0.74125?1.0 0.74 125?0.825 0.74125?0.825 gb/s 16 n/a n/a n/a n/a gb/s f gtxqrange2 qpll line rate range 2 1 9.8? 12.5 n/a 9.8? 10.3125 n/a n/a n/a gb/s 2 4.9?6.25 4.9?5.15625 n/a n/a gb/s 4 2.45?3.125 2.45?2.578125 n/a n/a gb/s 8 1.225?1.5625 1.225?1.2890625 n/a n/a gb/s 16 0.6125?0.78125 0.6125? 0.64453125 n/a n/a gb/s f gcpllrange gtx transceiver cpll frequency range 1.6?3.3 1.6?3.3 1.6?3.3 1.6?3.3 ghz f gcpllrange1 gtx transceiver qpll frequency range 1 5.93?8.0 5.93?8.0 5.93?6.6 5.93?6.6 ghz f gcpllrange2 gtx transceiver qpll frequency range 2 9.8?12.5 9.8?10.3125 n/a n/a ghz notes: 1. the -1l speed grade requires a 4-byte internal data width for operation above 5.0 gb/s. 2. data rates between 8.0 gb/s and 9.8 gb/s are not available. ta bl e 1 6 : gtx transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3 -2 -1 -1l f gtxdrpclk gtxdrpclk maximum frequency 150 150 125 125 mhz
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 10 integrated interface block for pci ex press designs switching characteristics more information and documentation on soluti ons for pci express designs can be found at: http://www.xilinx.com /technology/protoco ls/pciexpress.htm ta bl e 1 7 : gtx transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range 60 ? 650 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 40 50 60 % t lock clock recovery frequency acquisition time initial pll lock ?? ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock ?? s x-ref target - figure 3 figure 3: reference clock timing parameters ta bl e 1 8 : maximum performance for pci express designs symbol description speed grade units -3 -2 -1 -1l f pipeclk pipe clock maximum frequency 250 250 250 250 mhz f userclk user clock maximum frequency 500 500 250 250 mhz f userclk2 user clock 2 maximum frequency 250 250 250 250 mhz f drpclk drp clock maximum frequency 250 250 250 250 mhz d s 1 8 2_0 3 _021611 8 0 % 20 % t fclk t rclk
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 11 xadc specifications ta bl e 1 9 : xadc specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 5%, v refp =1.25v, v refn = 0v, adcclk = 26 mhz, t j = ?40c to 100c, typical values at t j =+40c adc accuracy (1) resolution 12 ? ? bits integral nonlinearity inl ? ? 2 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ? ? 1 lsbs offset error calibrated ? ? 4 lsbs gain error calibrated ? ? 0.4 % channel matching based on two individual adc instances with calibration enabled ? ? 10 lsbs sample rate 0.1 ? 1 ms/s signal to noise ratio snr f sample = 500ks/s, f in = 20khz 60 ? ? db rms code noise external 1.25v reference ? ? 2 lsbs on-chip reference ? 3 ? lsbs total harmonic distortion thd f sample = 500ks/s, f in = 20khz 75 ? ? db adc accuracy at extended temperatures (-55c to 125c) resolution 10 ? ? bits integral nonlinearity inl ? ? 1 lsb (at 10 bits) differential nonlinearity dnl no missing codes, guaranteed monotonic ? ? 1 analog inputs (2) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v auxiliary channel full resolution bandwidth frbw 250 ? ? khz on-chip sensors temperature sensor error t j = ?40c to 100c. ? ? 4 c t j = ?55c to +125c ? ? 6 c supply sensor error measurement range of v ccaux 1.8v 5% t j = ?40c to +100c ??1 % measurement range of v ccaux 1.8v 5% t j = ?55c to +125c ??2 % conversion rate (3) conversion time - continuous t conv number of adcclk cycles 26 ? 32 conversion time - event t conv number of clk cycles ? ? 21 drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 26 mhz dclk duty cycle 40 ? 60 %
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 12 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in kintex-7 devices. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the switching characteristics, page 15 . in each table, the i/o bank type is either high performance (hp) or high range (hr). xadc reference (4) external reference v refp externally supplied refer ence voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, t j = ?40c to 100c 1.2375 1.25 1.2625 v power requirements analog power supply v ccadc 1.71 1.8 1.89 v analog supply current i ccadc analog circuits in powered up state ? ? 20 ma notes: 1. offset and gain errors are removed by enabling the xadc automatic gain calibration feature. 2. see the adc chapter in ug480 : 7 series fpgas xadc user guide for a detailed description. 3. see the timing chapter in ug480 : 7 series fpgas xadc user guide for a detailed description. 4. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. on-chip reference variation is 1%. ta bl e 2 0 : networking applications interface performances description i/o bank type speed grade units -3 -2 -1 -1l sdr lvds transmitter (using oserdes; data_width = 4 to 8) hr 710 710 625 mb/s hp 710 710 625 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 10) hr 1055 800 667 mb/s hp 1600 1400 1250 mb/s sdr lvds receiver (sfi-4.1) (1) hr 710 710 625 mb/s hp 710 710 625 mb/s ddr lvds receiver (spi-4.2) (1) hr 1055 800 667 mb/s hp 1600 1400 1250 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specific dynamic phase-alignment (dpa) algorithms domina te deterministic performance. ta bl e 1 9 : xadc specifications (cont?d) parameter symbol comments/conditions min typ max units
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 13 ta bl e 2 1 : maximum physical interface (phy) rate for memory interfaces (ffg packages) (1) memory standard i/o bank type v ccaux_io speed grade units -3 -2 -1 -1l ddr3 hp 2.0v 1866 1600 mb/s hp 1.8v 1600 1333 1066 mb/s hr n/a 1066 1066 800 mb/s ddr3l hp 2.0v 1333 mb/s hp 1.8v 1333 1066 800 mb/s hr n/a 800 800 667 mb/s ddr2 hp 2.0v 800 800 800 mb/s hp 1.8v hr n/a qdr ii+ hp 2.0v 550 500 450 mhz hp 1.8v hr n/a 500 450 400 mhz rldram ii hp 2.0v 533 500 450 mhz hp 1.8v hr n/a rldram iii hp 2.0v mhz hp 1.8v mhz hr n/a n/a lpddr2 hp 2.0v mb/s hp 1.8v mb/s hr n/a mb/s notes: 1. advance performance numbers pending characterization on xilinx memory platforms designed according to the guidelines in the 7series fpgas memory interface solutions user guide .
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 14 ta bl e 2 2 : maximum physical interface (phy) rate for memory interfaces (fbg / sbg packages) (1) memory standard i/o bank type v ccaux_io (2) speed grade units -3 -2 -1 -1l ddr3 hp n/a 1333 1066 800 mb/s hr n/a 1066 800 800 mb/s ddr3l hp n/a 1066 800 667 mb/s hr n/a 800 800 667 mb/s ddr2 hp n/a 800 800 800 mb/s hr n/a 800 667 667 mb/s qdr ii+ hp n/a 550 500 450 mhz hr n/a 450 400 350 mhz rldram ii hp n/a 533 500 450 mhz hr n/a rldram iii hp n/a mhz hr n/a n/a lpddr2 hp n/a mb/s hr n/a mb/s notes: 1. advance performance numbers pending characterization on xilinx memory platforms designed according to the guidelines in the 7series fpgas memory interface solutions user guide . 2. fbg and sbg package types do not have separate v ccaux_io supply pins to adjust the pre-driver voltage of the hp i/o banks.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 15 switching characteristics all values represented in this data sheet are based on the advance speed specifications in ise? software. switching characteristics are specified on a per-speed- grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. all specifications are always representative of worst-case supply voltage and junction temperature conditions. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. ta b l e 2 3 correlates the current status of each kintex-7 device on a per speed grade basis. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all kintex-7 devices. ta b l e 2 3 : kintex-7 device speed grade designations device speed grade designations advance preliminary production xc7k70t -1l, -1, -2, -3 xc7k160t -1l, -1, -2, -3 xc7k325t -1l, -1, -2, -3 xc7k355t -1l, -1, -2, -3 xc7k410t -1l, -1, -2, -3 xc7k420t -1l, -1, -2, -3 xc7k480t -1l, -1, -2, -3
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 16 production silicon and ise software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta bl e 2 4 lists the production released kintex-7 device, speed grade, and the minimum corresponding supported speed specification version and ise software revisions. the ise softw are and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. iob pad input/output/3-state switching characteristics ta bl e 2 5 (3.3v high-range iob (hr)) and ta b l e 2 6 (1.8v high-performance iob (hp)) summarizes the values of standard- specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on the capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on th e capability of the selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. ta bl e 2 7 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 2 4 : kintex-7 device production software and speed specification release device speed grade designations -3 -2 -1 -1l xc7k70t xc7k160t xc7k325t xc7k355t xc7k410t xc7k420t xc7k480t notes: 1. blank entries indicate a device and/or speed grade in advance or preliminary status. ta bl e 2 5 : 3.3v iob high range (hr) switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l lvds_25 (1) 1.30 1.38 1.50 1.14 1.23 1.37 1.14 1.23 1.37 ns mini_lvds_25 1.35 1.41 1.50 0. 85 0.88 0.94 0.85 0.88 0.94 ns blvds_25 (1) 0.71 0.76 0.83 1.14 1.23 1.37 1.14 1.23 1.37 ns rsds_25 (point to point) (1) 1.26 1.33 1.43 1.14 1.24 1.38 1.14 1.24 1.38 ns ppds_25 (1) 1.22 1.29 1.39 1.14 1.23 1.38 1.14 1.23 1.38 ns tmds_33 (1) 0.99 1.10 1.26 1.20 1.30 1.44 1.20 1.30 1.44 ns pci33_3 (1) 1.78 1.96 2.23 2.28 2.28 2.29 2.28 2.28 2.29 ns hsul_12 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns diff_hsul_12 0.85 0.89 0.94 0. 85 0.88 0.94 0.85 0.88 0.94 ns
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 17 hstl_i_s 0.41 0.47 0.56 0.78 0.86 0.98 0.78 0.86 0.98 ns hstl_ii_s 0.41 0.47 0.56 0.6 6 0.73 0.82 0.66 0.73 0.82 ns hstl_i_18_s 0.44 0.51 0.62 0. 74 0.82 0.93 0.74 0.82 0.93 ns hstl_ii_18_s 0.44 0.51 0.62 0.8 3 0.97 1.17 0.83 0.97 1.17 ns diff_hstl_i_s 0.45 0. 52 0.62 0.68 0.75 0. 86 1.21 1.30 1.44 ns diff_hstl_ii_s 0.45 0.52 0.62 0 .65 0.72 0.83 1.20 1.30 1.46 ns diff_hstl_i_18_s 0.46 0.53 0.64 0.68 0.75 0. 86 1.23 1.32 1.46 ns diff_hstl_ii_18_s 0. 46 0.53 0.64 0.65 0.72 0.83 1.25 1.36 1.51 ns hstl_i_f 0.41 0.47 0.56 0.78 0.86 0.98 0.78 0.86 0.98 ns hstl_ii_f 0.41 0.47 0.56 0.6 6 0.73 0.82 0.66 0.73 0.82 ns hstl_i_18_f 0.44 0.51 0.62 0. 74 0.82 0.93 0.74 0.82 0.93 ns hstl_ii_18_f 0.44 0.51 0.62 0.8 3 0.97 1.17 0.83 0.97 1.17 ns diff_hstl_i_f 0.45 0. 52 0.62 0.68 0.75 0. 86 1.21 1.30 1.44 ns diff_hstl_ii_f 0.45 0.52 0.62 0 .65 0.72 0.83 1.20 1.30 1.46 ns diff_hstl_i_18_f 0.46 0.53 0.64 0.68 0.75 0. 86 1.23 1.32 1.46 ns diff_hstl_ii_18_f 0. 46 0.53 0.64 0.65 0.72 0.83 1.25 1.36 1.51 ns lvcmos33, slow, 4 ma 1.60 1.69 1.8 3 4.64 4.93 5.37 4.64 4.93 5.37 ns lvcmos33, slow, 8 ma 1.60 1.69 1.8 3 4.67 4.96 5.38 4.67 4.96 5.38 ns lvcmos33, slow, 12 ma 1.60 1.69 1. 83 3.78 3.97 4.27 3.78 3.97 4.27 ns lvcmos33, slow, 16 ma 1.60 1.69 1. 83 3.76 3.96 4.25 3.76 3.96 4.25 ns lvcmos33, fast, 4 ma 1.60 1.69 1.8 3 4.58 4.84 5.23 4.58 4.84 5.23 ns lvcmos33, fast, 8 ma 1.60 1.69 1.8 3 4.58 4.84 5.22 4.58 4.84 5.22 ns lvcmos33, fast, 12 ma 1.60 1.69 1. 83 3.69 3.88 4.17 3.69 3.88 4.17 ns lvcmos33, fast, 16 ma 1.60 1.69 1. 83 3.66 3.85 4.14 3.66 3.85 4.14 ns lvcmos25, slow, 4 ma 1.39 1.50 1.6 7 4.51 4.72 5.05 4.51 4.72 5.05 ns lvcmos25, slow, 8 ma 1.39 1.50 1.6 7 4.48 4.74 5.12 4.48 4.74 5.12 ns lvcmos25, slow, 12 ma 1.39 1.50 1. 67 3.74 3.95 4.27 3.74 3.95 4.27 ns lvcmos25, slow, 16 ma 1.39 1.50 1. 67 3.73 3.94 4.27 3.73 3.94 4.27 ns lvcmos25, fast, 4 ma 1.39 1.50 1.6 7 4.42 4.64 4.97 4.42 4.64 4.97 ns lvcmos25, fast, 8 ma 1.39 1.50 1.6 7 4.42 4.65 5.00 4.42 4.65 5.00 ns lvcmos25, fast, 12 ma 1.39 1.50 1. 67 3.66 3.86 4.15 3.66 3.86 4.15 ns lvcmos25, fast, 16 ma 1.39 1.50 1. 67 3.66 3.86 4.18 3.66 3.86 4.18 ns lvcmos18, slow, 4 ma 0.44 0.51 0.6 2 3.36 3.61 3.99 3.36 3.61 3.99 ns lvcmos18, slow, 8 ma 0.44 0.51 0.6 2 3.37 3.62 4.00 3.37 3.62 4.00 ns lvcmos18, slow, 12 ma 0.44 0.51 0. 62 2.87 3.10 3.44 2.87 3.10 3.44 ns lvcmos18, slow, 16 ma 0.44 0.51 0. 62 2.87 3.10 3.44 2.87 3.10 3.44 ns lvcmos18, slow, 24 ma (1) 0.44 0.51 0.62 2.87 3.10 3.44 2.87 3.10 3.44 ns ta bl e 2 5 : 3.3v iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 18 lvcmos18, fast, 4 ma 0.44 0.51 0.6 2 3.34 3.58 3.95 3.34 3.58 3.95 ns lvcmos18, fast, 8 ma 0.44 0.51 0.6 2 3.35 3.59 3.94 3.35 3.59 3.94 ns lvcmos18, fast, 12 ma 0.44 0.51 0. 62 2.81 3.04 3.39 2.81 3.04 3.39 ns lvcmos18, fast, 16 ma 0.44 0.51 0. 62 2.81 3.04 3.39 2.81 3.04 3.39 ns lvcmos18, fast, 24 ma (1) 0.44 0.51 0.62 2.81 3.04 3.39 2.81 3.04 3.39 ns lvcmos15, slow, 4 ma 0.46 0.52 0.6 1 3.45 3.70 4.09 3.45 3.70 4.09 ns lvcmos15, slow, 8 ma 0.46 0.52 0.6 1 3.41 3.68 4.09 3.41 3.68 4.09 ns lvcmos15, slow, 12 ma 0.46 0.52 0. 61 3.07 3.31 3.68 3.07 3.31 3.68 ns lvcmos15, slow, 16 ma 0.46 0.52 0. 61 3.07 3.31 3.68 3.07 3.31 3.68 ns lvcmos15, fast, 4 ma 0.46 0.52 0.6 1 3.44 3.99 4.82 3.44 3.99 4.82 ns lvcmos15, fast, 8 ma 0.46 0.52 0.6 1 3.39 3.66 4.08 3.39 3.66 4.08 ns lvcmos15, fast, 12 ma 0.46 0.52 0. 61 3.05 3.28 3.61 3.05 3.28 3.61 ns lvcmos15, fast, 16 ma 0.46 0.52 0. 61 3.05 3.28 3.61 3.05 3.28 3.61 ns lvcmos12, slow, 4 ma 0.53 0.59 0.6 8 3.45 3.73 4.15 3.45 3.73 4.15 ns lvcmos12, slow, 8 ma 0.53 0.59 0.6 8 3.12 3.31 3.59 3.12 3.31 3.59 ns lvcmos12, slow, 12 ma (1) 0.53 0.59 0.68 3.12 3.31 3.59 3.12 3.31 3.59 ns lvcmos12, fast, 4 ma 0.53 0.59 0.6 8 3.46 3.74 4.18 3.46 3.74 4.18 ns lvcmos12, fast, 8 ma 0.53 0.59 0.6 8 3.05 3.27 3.60 3.05 3.27 3.60 ns lvcmos12, fast, 12 ma (1) 0.53 0.59 0.68 3.05 3.27 3.60 3.05 3.27 3.60 ns sstl135_s 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns sstl135_ii_s 0.85 0.89 0.94 0.8 5 0.88 0.94 0.85 0.88 0.94 ns sstl15_s 0.85 0.89 0.94 0.85 0 .88 0.94 0.85 0.88 0.94 ns sstl15_ii_s 0.60 0.67 0.79 0. 66 0.73 0.82 0.66 0.73 0.82 ns sstl18_i_s 0.85 0.89 0.94 0.7 5 0.82 0.94 0.75 0.82 0.94 ns sstl18_ii_s 0.85 0.89 0.94 0. 68 0.75 0.85 0.68 0.75 0.85 ns diff_sstl135_s 0.85 0. 89 0.94 0.85 0.88 0. 94 0.85 0.88 0.94 ns diff_sstl135_ii_s 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns diff_sstl15_s 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns diff_sstl15_ii_s 0.85 0.89 0.94 0.66 0.73 0. 82 0.66 0.73 0.82 ns diff_sstl18_i_s 0.47 0.53 0.62 0.67 0.75 0.86 0.67 0.75 0.86 ns diff_sstl18_ii_s 0.47 0.53 0.62 0.65 0.73 0. 83 0.65 0.73 0.83 ns ta bl e 2 5 : 3.3v iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 19 sstl135_f 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns sstl135_ii_f 0.85 0.89 0.94 0.8 5 0.88 0.94 0.85 0.88 0.94 ns sstl15_f 0.85 0.89 0.94 0.85 0 .88 0.94 0.85 0.88 0.94 ns sstl15_ii_f 0.60 0.67 0.79 0. 66 0.73 0.82 0.66 0.73 0.82 ns sstl18_i_f 0.85 0.89 0.94 0.7 5 0.82 0.94 0.75 0.82 0.94 ns sstl18_ii_f 0.85 0.89 0.94 0. 68 0.75 0.85 0.68 0.75 0.85 ns diff_sstl135_f 0.85 0. 89 0.94 0.85 0.88 0. 94 0.85 0.88 0.94 ns diff_sstl135_ii_f 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns diff_sstl15_f 0.85 0.89 0.94 0.85 0.88 0.94 0.85 0.88 0.94 ns diff_sstl15_ii_f 0.85 0.89 0.94 0.66 0.73 0. 82 0.66 0.73 0.82 ns diff_sstl18_i_f 0.47 0.53 0.62 0.67 0.75 0.86 0.67 0.75 0.86 ns diff_sstl18_ii_f 0.47 0.53 0.62 0.65 0.73 0. 83 0.65 0.73 0.83 ns notes: 1. this i/o standard is only available in the 3.3v high-range (hr) banks. ta bl e 2 6 : 1.8v iob high performance (hp) switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l lvds 0.77 0.86 0.99 1.21 1. 29 1.41 1.21 1.29 1.41 ns hsul_12 0.71 0.83 0.96 1.23 1.32 1.46 1.23 1.32 1.46 ns diff_hsul_12 0.71 0.83 0.96 1. 23 1.32 1.46 1.23 1.32 1.46 ns hstl_i_s 0.74 0.83 0.96 1.21 1.30 1.44 1.21 1.30 1.44 ns hstl_ii_s 0.74 0.83 0.96 1.2 0 1.31 1.46 1.20 1.31 1.46 ns hstl_iii_s 0.74 0.83 0.96 1. 18 1.28 1.43 1.18 1.28 1.43 ns hstl_i_18_s 0.74 0.83 0.96 1. 23 1.32 1.46 1.23 1.32 1.46 ns hstl_ii_18_s 0.74 0.83 0.96 1.2 5 1.36 1.52 1.25 1.36 1.52 ns hstl_iii_18_s 0.74 0.83 0.96 1. 19 1.29 1.43 1.19 1.29 1.43 ns hstl_i_12_s 0.74 0.83 0.96 1. 23 1.33 1.48 1.23 1.33 1.48 ns hstl_i_dci_s 0.74 0.83 0.96 1. 19 1.28 1.41 1.19 1.28 1.41 ns hstl_ii_dci_s 0.74 0.83 0.96 1. 15 1.25 1.40 1.15 1.25 1.40 ns hstl_ii_t_dci_s 0.74 0.83 0.96 1.17 1.26 1.39 1. 17 1.26 1.39 ns hstl_iii_dci_s 0.74 0.83 0.96 1.12 1.21 1.36 1. 12 1.21 1.36 ns hstl_i_dci_18_s 0.74 0.83 0.96 1.19 1.28 1.41 1. 19 1.28 1.41 ns hstl_ii_dci_18_s 0.74 0.83 0.96 1.13 1.22 1.35 1. 13 1.22 1.35 ns hstl_ii _t_dci_18_s 0.74 0.83 0. 96 1.19 1.28 1.41 1.19 1.28 1.41 ns hstl_iii_dci_18_s 0.74 0.83 0.9 6 1.20 1.28 1.42 1.20 1.28 1.42 ns diff_hstl_i_s 0.77 0. 86 0.99 1.21 1.30 1. 44 1.21 1.30 1.44 ns ta bl e 2 5 : 3.3v iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 20 diff_hstl_ii_s 0.77 0.86 0.99 1 .20 1.31 1.46 1.20 1.31 1.46 ns diff_hstl_i_dci_s 0. 77 0.86 0.99 1.17 1.26 1.39 1.17 1.26 1.39 ns diff_hstl_ii_dci_s 0. 77 0.86 0.99 1.15 1.25 1.40 1.15 1.25 1.40 ns diff_hstl_i_18_s 0.77 0.86 0.99 1.23 1.32 1. 46 1.23 1.32 1.46 ns diff_hstl_ii_18_s 0. 77 0.86 0.99 1.25 1.36 1.52 1.25 1.36 1.52 ns diff_hstl_i_dci_18_s 0. 77 0.86 0.99 1.19 1.28 1.41 1.19 1.28 1.41 ns diff_hstl_ii_dci_18_s 0. 77 0.86 0.99 1.13 1.22 1.35 1.13 1.22 1.35 ns diff_hstl_ii _t_dci_18_s 0.77 0.86 0 .99 1.19 1.28 1.41 1.19 1.28 1.41 ns hstl_i_f 0.74 0.83 0.96 1.21 1.30 1.44 1.21 1.30 1.44 ns hstl_ii_f 0.74 0.83 0.96 1.2 0 1.31 1.46 1.20 1.31 1.46 ns hstl_iii_f 0.74 0.83 0.96 1. 18 1.28 1.43 1.18 1.28 1.43 ns hstl_i_18_f 0.74 0.83 0.96 1. 23 1.32 1.46 1.23 1.32 1.46 ns hstl_ii_18_f 0.74 0.83 0.96 1.2 5 1.36 1.52 1.25 1.36 1.52 ns hstl_iii_18_f 0.74 0.83 0.96 1. 19 1.29 1.43 1.19 1.29 1.43 ns hstl_i_12_f 0.74 0.83 0.96 1. 23 1.33 1.48 1.23 1.33 1.48 ns hstl_i_dci_f 0.74 0.83 0.96 1. 19 1.28 1.41 1.19 1.28 1.41 ns hstl_ii_dci_f 0.74 0.83 0.96 1. 15 1.25 1.40 1.15 1.25 1.40 ns hstl_ii_t_dci_f 0.74 0.83 0.96 1.17 1.26 1.39 1. 17 1.26 1.39 ns hstl_iii_dci_f 0.74 0.83 0.96 1.12 1.21 1.36 1. 12 1.21 1.36 ns hstl_i_dci_18_f 0.74 0.83 0.96 1.19 1.28 1.41 1. 19 1.28 1.41 ns hstl_ii_dci_18_f 0.74 0.83 0.96 1.13 1.22 1.35 1. 13 1.22 1.35 ns hstl_ii _t_dci_18_f 0.74 0.83 0. 96 1.19 1.28 1.41 1.19 1.28 1.41 ns hstl_iii_dci_18_f 0.74 0.83 0.9 6 1.20 1.28 1.42 1.20 1.28 1.42 ns diff_hstl_i_f 0.77 0. 86 0.99 1.21 1.30 1. 44 1.21 1.30 1.44 ns diff_hstl_ii_f 0.77 0.86 0.99 1 .20 1.31 1.46 1.20 1.31 1.46 ns diff_hstl_i_dci_f 0. 77 0.86 0.99 1.17 1.26 1.39 1.17 1.26 1.39 ns diff_hstl_ii_dci_f 0. 77 0.86 0.99 1.15 1.25 1.40 1.15 1.25 1.40 ns diff_hstl_i_18_f 0.77 0.86 0.99 1.23 1.32 1. 46 1.23 1.32 1.46 ns diff_hstl_ii_18_f 0. 77 0.86 0.99 1.25 1.36 1.52 1.25 1.36 1.52 ns diff_hstl_i_dci_18_f 0. 77 0.86 0.99 1.19 1.28 1.41 1.19 1.28 1.41 ns diff_hstl_ii_dci_18_f 0. 77 0.86 0.99 1.13 1.22 1.35 1.13 1.22 1.35 ns diff_hstl_ii _t_dci_18_f 0.77 0.86 0 .99 1.19 1.28 1.41 1.19 1.28 1.41 ns lvcmos18, slow, 2 ma 0.50 0.56 0.6 5 3.52 3.74 4.07 3.52 3.74 4.07 ns lvcmos18, slow, 4 ma 0.50 0.56 0.6 5 2.33 2.47 2.68 2.33 2.47 2.68 ns lvcmos18, slow, 6 ma 0.50 0.56 0.6 5 1.92 2.04 2.20 1.92 2.04 2.20 ns lvcmos18, slow, 8 ma 0.50 0.56 0.6 5 1.68 1.77 1.90 1.68 1.77 1.90 ns lvcmos18, slow, 12 ma 0.50 0.56 0. 65 1.57 1.66 1.79 1.57 1.66 1.79 ns lvcmos18, slow, 16 ma 0.50 0.56 0. 65 1.53 1.63 1.77 1.53 1.63 1.77 ns ta bl e 2 6 : 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 21 lvcmos18, fast, 2 ma 0.50 0.56 0.6 5 3.34 3.53 3.82 3.34 3.53 3.82 ns lvcmos18, fast, 4 ma 0.50 0.56 0.6 5 2.19 2.31 2.49 2.19 2.31 2.49 ns lvcmos18, fast, 6 ma 0.50 0.56 0.6 5 1.80 1.90 2.06 1.80 1.90 2.06 ns lvcmos18, fast, 8 ma 0.50 0.56 0.6 5 1.58 1.66 1.78 1.58 1.66 1.78 ns lvcmos18, fast, 12 ma 0.50 0.56 0. 65 1.41 1.51 1.65 1.41 1.51 1.65 ns lvcmos18, fast, 16 ma 0.50 0.56 0. 65 1.37 1.46 1.59 1.37 1.46 1.59 ns lvcmos15, slow, 2 ma 0.58 0.66 0.7 7 2.86 3.16 3.59 2.86 3.16 3.59 ns lvcmos15, slow, 4 ma 0.58 0.66 0.7 7 2.15 2.33 2.59 2.15 2.33 2.59 ns lvcmos15, slow, 6 ma 0.58 0.66 0.7 7 1.74 1.94 2.24 1.74 1.94 2.24 ns lvcmos15, slow, 8 ma 0.58 0.66 0.7 7 1.52 1.66 1.87 1.52 1.66 1.87 ns lvcmos15, slow, 12 ma 0.58 0.66 0. 77 1.47 1.60 1.79 1.47 1.60 1.79 ns lvcmos15, slow, 16 ma 0.58 0.66 0. 77 1.41 1.53 1.71 1.41 1.53 1.71 ns lvcmos15, fast, 2 ma 0.58 0.66 0.7 7 2.87 3.16 3.58 2.87 3.16 3.58 ns lvcmos15, fast, 4 ma 0.58 0.66 0.7 7 1.98 2.12 2.32 1.98 2.12 2.32 ns lvcmos15, fast, 6 ma 0.58 0.66 0.7 7 1.51 1.71 2.02 1.51 1.71 2.02 ns lvcmos15, fast, 8 ma 0.58 0.66 0.7 7 1.47 1.59 1.76 1.47 1.59 1.76 ns lvcmos15, fast, 12 ma 0.58 0.66 0. 77 1.37 1.48 1.64 1.37 1.48 1.64 ns lvcmos15, fast, 16 ma 0.58 0.66 0. 77 1.36 1.47 1.64 1.36 1.47 1.64 ns lvcmos12, slow, 2 ma 0.66 0.73 0.8 4 2.63 2.83 3.13 2.63 2.83 3.13 ns lvcmos12, slow, 4 ma 0.66 0.73 0.8 4 2.03 2.20 2.45 2.03 2.20 2.45 ns lvcmos12, slow, 6 ma 0.66 0.73 0.8 4 1.60 1.77 2.01 1.60 1.77 2.01 ns lvcmos12, slow, 8 ma 0.66 0.73 0.8 4 1.56 1.69 1.88 1.56 1.69 1.88 ns lvcmos12, fast, 2 ma 0.66 0.73 0.8 4 2.26 2.49 2.83 2.26 2.49 2.83 ns lvcmos12, fast, 4 ma 0.66 0.73 0.8 4 1.61 1.81 2.10 1.61 1.81 2.10 ns lvcmos12, fast, 6 ma 0.66 0.73 0.8 4 1.47 1.58 1.76 1.47 1.58 1.76 ns lvcmos12, fast, 8 ma 0.66 0.73 0.8 4 1.41 1.52 1.69 1.41 1.52 1.69 ns lvdci_18 0.50 0.56 0.65 1.73 1.87 2.07 1.73 1.87 2.07 ns lvdci_15 0.58 0.66 0.77 1.55 1.68 1.87 1.55 1.68 1.87 ns lvdci_dv2_18 0.50 0.56 0.65 1.41 1.52 1.67 1.41 1.52 1.67 ns lvdci_dv2_15 0.58 0.66 0.77 1.40 1.48 1.59 1.40 1.48 1.59 ns hslvdci_18 0.74 0.83 0.96 1.73 1.87 2.07 1.73 1.87 2.07 ns hslvdci_15 0.74 0.83 0.96 1.55 1.68 1.87 1.55 1.68 1.87 ns sstl18_i_s 0.74 0.83 0.96 1.2 3 1.32 1.46 1.23 1.32 1.46 ns sstl18_ii_s 0.74 0.83 0.96 1. 16 1.26 1.40 1.16 1.26 1.40 ns sstl18_i_dci_s 0.74 0.83 0.96 1. 17 1.26 1.39 1.17 1.26 1.39 ns sstl18_ii_dci_s 0.74 0.83 0.96 1.14 1.23 1.36 1. 14 1.23 1.36 ns sstl18_ii_t_dci_s 0. 74 0.83 0.96 1.17 1.26 1.39 1.17 1.26 1.39 ns sstl15_s 0.74 0.83 0.96 1.19 1 .28 1.43 1.19 1.28 1.43 ns ta bl e 2 6 : 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 22 sstl15_dci_s 0.74 0.83 0.96 1. 18 1.27 1.40 1.18 1.27 1.40 ns sstl15_t_dci_s 0.74 0.83 0.96 1 .18 1.27 1.40 1.18 1.27 1.40 ns sstl135_s 0.74 0.83 0.96 1.19 1.28 1.43 1.19 1.28 1.43 ns sstl135_dci_s 0.74 0.83 0.96 1. 18 1.27 1.40 1.18 1.27 1.40 ns sstl135_t_dci_s 0.74 0.83 0.96 1.18 1.27 1.40 1. 18 1.27 1.40 ns sstl12_s 0.71 0.83 0.96 1.23 1 .32 1.46 1.23 1.32 1.46 ns sstl12_dci_s 0.71 0.83 0.96 1. 23 1.32 1.46 1.23 1.32 1.46 ns sstl12_t_dci_s 0.71 0.83 0.96 1 .23 1.32 1.46 1.23 1.32 1.46 ns diff_sstl18_i_s 0.77 0.86 0.99 1.23 1.32 1.46 1.23 1.32 1.46 ns diff_sstl18_ii_s 0.77 0.86 0.99 1.16 1.26 1. 40 1.16 1.26 1.40 ns diff_sstl18_i_dci_s 0. 77 0.86 0.99 1.17 1.26 1.39 1.17 1.26 1.39 ns diff_sstl18_ii_dci_s 0. 77 0.86 0.99 1.14 1.23 1.36 1.14 1.23 1.36 ns diff_sstl18_ii_t_ dci_s 0.77 0.86 0.99 1.17 1. 26 1.39 1.17 1.26 1.39 ns diff_sstl15_s 0.74 0.83 0.96 1.19 1.28 1.43 1.19 1.28 1.43 ns diff_sstl15_dci_s 0.74 0.83 0.96 1.18 1.27 1. 40 1.18 1.27 1.40 ns diff_sstl15_t_dci_s 0. 74 0.83 0.96 1.18 1.27 1.40 1.18 1.27 1.40 ns diff_sstl135_s 0.74 0. 83 0.96 1.19 1.28 1. 43 1.19 1.28 1.43 ns diff_sstl135_dci_s 0. 74 0.83 0.96 1.18 1.27 1.40 1.18 1.27 1.40 ns diff_sstl135_t_dci_s 0. 74 0.83 0.96 1.18 1.27 1.40 1.18 1.27 1.40 ns diff_sstl12_s 0.71 0.83 0.96 1.23 1.32 1.46 1.23 1.32 1.46 ns diff_sstl12_dci_s 0.71 0.83 0.96 1.23 1.32 1. 46 1.23 1.32 1.46 ns diff_sstl12_t_dci_s 0. 71 0.83 0.96 1.23 1.32 1.46 1.23 1.32 1.46 ns sstl18_i_f 0.74 0.83 0.96 1.2 3 1.32 1.46 1.23 1.32 1.46 ns sstl18_ii_f 0.74 0.83 0.96 1. 16 1.26 1.40 1.16 1.26 1.40 ns sstl18_i_dci_f 0.74 0.83 0.96 1. 17 1.26 1.39 1.17 1.26 1.39 ns sstl18_ii_dci_f 0.74 0.83 0.96 1.14 1.23 1.36 1. 14 1.23 1.36 ns sstl18_ii_t_dci_f 0. 74 0.83 0.96 1.17 1.26 1.39 1.17 1.26 1.39 ns sstl15_f 0.74 0.83 0.96 1.19 1 .28 1.43 1.19 1.28 1.43 ns sstl15_dci_f 0.74 0.83 0.96 1. 18 1.27 1.40 1.18 1.27 1.40 ns sstl15_t_dci_f 0.74 0.83 0.96 1 .18 1.27 1.40 1.18 1.27 1.40 ns sstl135_f 0.74 0.83 0.96 1.19 1.28 1.43 1.19 1.28 1.43 ns sstl135_dci_f 0.74 0.83 0.96 1. 18 1.27 1.40 1.18 1.27 1.40 ns sstl135_t_dci_f 0.74 0.83 0.96 1.18 1.27 1.40 1. 18 1.27 1.40 ns sstl12_f 0.71 0.83 0.96 1.23 1 .32 1.46 1.23 1.32 1.46 ns sstl12_dci_f 0.71 0.83 0.96 1. 23 1.32 1.46 1.23 1.32 1.46 ns sstl12_t_dci_f 0.71 0.83 0.96 1 .23 1.32 1.46 1.23 1.32 1.46 ns diff_sstl18_i_f 0.77 0.86 0.99 1.23 1.32 1.46 1.23 1.32 1.46 ns diff_sstl18_ii_f 0.77 0.86 0.99 1.16 1.26 1. 40 1.16 1.26 1.40 ns ta bl e 2 6 : 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 23 diff_sstl18_i_dci_f 0. 77 0.86 0.99 1.17 1.26 1.39 1.17 1.26 1.39 ns diff_sstl18_ii_dci_f 0. 77 0.86 0.99 1.14 1.23 1.36 1.14 1.23 1.36 ns diff_sstl18_ii_t_ dci_f 0.77 0.86 0.99 1.17 1. 26 1.39 1.17 1.26 1.39 ns diff_sstl15_f 0.74 0.83 0.96 1.19 1.28 1.43 1.19 1.28 1.43 ns diff_sstl15_dci_f 0.74 0.83 0.96 1.18 1.27 1. 40 1.18 1.27 1.40 ns diff_sstl15_t_dci_f 0. 74 0.83 0.96 1.18 1.27 1.40 1.18 1.27 1.40 ns diff_sstl135_f 0.74 0. 83 0.96 1.19 1.28 1. 43 1.19 1.28 1.43 ns diff_sstl135_dci_f 0. 74 0.83 0.96 1.18 1.27 1.40 1.18 1.27 1.40 ns diff_sstl135_t_dci_f 0. 74 0.83 0.96 1.18 1.27 1.40 1.18 1.27 1.40 ns diff_sstl12_f 0.71 0.83 0.96 1.23 1.32 1.46 1.23 1.32 1.46 ns diff_sstl12_dci_f 0.71 0.83 0.96 1.23 1.32 1. 46 1.23 1.32 1.46 ns diff_sstl12_t_dci_f 0. 71 0.83 0.96 1.23 1.32 1.46 1.23 1.32 1.46 ns notes: 1. this i/o standard is only available in the 1.8v high-performance (hp) banks. ta bl e 2 7 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -3 -2 -1 -1l t iotphz t input to pad high-impedance 2.80 2.83 2.85 ns ta bl e 2 6 : 1.8v iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 24 i/o standard adjustment measurement methodology input delay measurements ta bl e 2 8 shows the test setup parameters used for measuring input delay. ta bl e 2 8 : input delay measurement methodology description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(5) v ref (1)(3)(5) lvttl lvttl 0 3.3 1.65 ? lvcmos, 3.3v lvcmos33 0 3.3 1.65 ? lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 sstl (stub terminated transceiver logic), 1.5v and 1.35v sstl15, sstl135 v ref ?1.00 v ref +1.00 v ref 0.75, 0.675 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 lvds (low-voltage differential signaling), hr i/o banks lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ? lvds (low-voltage differential signalin g), hp i/o banks lvds 1.2 ? 0.125 1.2 + 0.125 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as for hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 4 . 6. the value given is the differential input voltage.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 25 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4" of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 4 and figure 5 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 2 9 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 4 figure 4: single ended test setup v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 1 8 2_04_021611 x-ref target - figure 5 figure 5: differential test setup r ref v mea s + ? c ref fpga o u tp u t d s 1 8 2_05_021611 ta bl e 2 9 : output delay measurement methodology description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.75 0 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl15 sstl15 50 0 v ref 0.75 sstl135 sstl135 50 0 v ref 0.675 lvds (low-voltage differential signaling), 2.5v lvds_25 100 0 0 (2) 1.2 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 1m 0 0.9 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 1m 0 0.75 0
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 26 input/output logic switching characteristics hstl (high-speed transceiver logic), class i & ii, with dci hstl_i_dci, hstl_ii_dci 50 0 v ref 0.75 hstl, class i & ii, 1.8v, with dci hstl_i_dci_18, hstl_ii_dci_18 50 0 v ref 0.9 sstl (stub series termi.logic), class i & ii, 1.8v, with dci sstl18_i_dci, sstl18_ii_dci 50 0 v ref 0.9 sstl15, with dci sstl15_dci 50 0 v ref 0.675 sstl135, with dci sstl135_dci 50 0 v ref 0.75 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. ta bl e 3 0 : ilogic switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to clk 0.31/ 0.05 0.36/ 0.06 0.44/ 0.07 ns t isrck /t icksr sr pin setup/hold with respect to clk 1.00/ ?0.14 1.15/ ?0.14 1.39/ ?0.14 ns t idocke2 /t iockde2 d pin setup/hold with respect to clk without delay (hp i/o banks only) 0.11/ 0.38 0.13/ 0.42 0.15/ 0.49 ns t idockde2 /t iockdde2 ddly pin setup/hold with respect to clk (using idelay) (hp i/o banks only) 0.14/ 0.29 0.17/ 0.32 0.20/ 0.37 ns t idocke3 /t iockde3 d pin setup/hold with respect to clk without delay (hr i/o banks only) 0.11/ 0.38 0.13/ 0.42 0.15/ 0.49 ns t idockde3 /t iockdde3 ddly pin setup/hold with respect to clk (using idelay) (hr i/o banks only) 0.14/ 0.29 0.17/ 0.32 0.20/ 0.37 ns combinatorial t idie2 d pin to o pin propagation delay, no delay (hp i/o banks only) 0.19 0.21 0.24 ns t idide2 ddly pin to o pin propagation delay (using idelay) (hp i/o banks only) 0.22 0.24 0.28 ns t idie3 d pin to o pin propagation delay, no delay (hr i/o banks only) 0.19 0.21 0.24 ns t idide3 ddly pin to o pin propagation delay (using idelay) (hr i/o banks only) 0.22 0.24 0.28 ns sequential delays t idloe2 d pin to q1 pin using flip-flop as a latch without delay (hp i/o banks only) 0.48 0.54 0.62 ns t idlode2 ddly pin to q1 pin using flip-flop as a latch (using idelay) (hp i/o banks only) 0.51 0.57 0.66 ns t idloe3 d pin to q1 pin using flip-flop as a latch without delay (hr i/o banks only) 0.48 0.54 0.62 ns t idlode3 ddly pin to q1 pin using flip-flop as a latch (using idelay) (hr i/o banks only) 0.51 0.57 0.66 ns t ickq clk to q outputs 0.55 0.61 0.70 ns ta bl e 2 9 : output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v)
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 27 t rq_ilogice2 sr pin to oq/tq out (hp i/o banks only) 1.12 1.29 1.54 ns t gsrq_ilogice2 global set/reset to q outputs (hp i/o banks only) 7.67 7.67 10.61 ns t rq_ilogice3 sr pin to oq/tq out (hr i/o banks only) 1.12 1.29 1.54 ns t gsrq_ilogice3 global set/reset to q outputs (hr i/o banks only) 7.67 7.67 10.61 ns set/reset t rpw_ilogice2 minimum pulse width, sr inputs (hp i/o banks only) 0.63 0.66 0.71 ns, min t rpw_ilogice3 minimum pulse width, sr inputs ( hr i/o banks only) 0.82 1.00 1.26 ns, min ta bl e 3 1 : ologic switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0.55/ ?0.22 0.61/ ?0.22 0.71/ ?0.22 ns t ooceck /t ockoce oce pin setup/hold with respect to clk 0.13/ ?0.06 0.15/ ?0.06 0.18/ ?0.06 ns t osrck /t ocksr sr pin setup/hold with respect to clk 0.54/ ?0.20 0.64/ ?0.20 0.79/ ?0.20 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk 0.53/ ?0.21 0.59/ ?0.21 0.69/ ?0.21 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.12/ ?0.05 0.14/ ?0.05 0.17/ ?0.05 ns combinatorial t odq d1 to oq out or t1 to tq out 0.78 0.88 1.03 ns sequential delays t ockq clk to oq/tq out 0.31 0.35 0.41 ns t rq_ologice2 sr pin to oq/tq out (hp i/o banks only) 0.56 0.64 0.76 ns t gsrq_ologice2 global set/reset to q outputs (hp i/o banks only) 7.67 7.67 10.61 ns t rq_ologice3 sr pin to oq/tq out (hr i/o banks only) 0.56 0.64 0.76 ns t gsrq_ologice3 global set/reset to q outputs (hr i/o banks only) 7.67 7.67 10.61 ns set/reset t rpw_ologice2 minimum pulse width, sr inputs (h p i/o banks only) 0.63 0.66 0.71 ns, min t rpw_ologice3 minimum pulse width, sr inputs (hr i/o banks only) 0.82 1.00 1.26 ns, min ta bl e 3 0 : ilogic switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 28 input serializer/deserializer switching characteristics ta bl e 3 2 : iserdes switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.13/ 0.11 0.15/ 0.12 0.18/ 0.15 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.22/ ?0.04 0.26/ ?0.04 0.32/ ?0.04 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) 0.06/ 0.14 0.06/ 0.15 0.07/ 0.18 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk 0.02/ 0.12 0.03/ 0.14 0.03/ 0.17 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using idelay) (1) 0.05/ 0.09 0.06/ 0.10 0.08/ 0.12 ns t isdck_d_ddr /t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode 0.02/ 0.12 0.03/ 0.14 0.03/ 0.17 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using idelay) (1) 0.05/ 0.09 0.06/ 0.10 0.08/ 0.12 ns sequential delays t iscko_q clkdiv to out at q pin 0.59 0.66 0.76 ns propagation delays t isdo_do d input to do output pin 0.22 0.24 0.28 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in trace report.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 29 output serializer/deserializ er switching characteristics ta bl e 3 3 : oserdes switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkdiv 0.48/ ?0.21 0.54/ ?0.21 0.63/ ?0.21 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0.53/ ?0.22 0.59/ ?0.22 0.69/ ?0.22 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.48/ ?0.22 0.56/ ?0.22 0.68/ ?0.22 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.13/ ?0.06 0.15/ ?0.06 0.18/ ?0.06 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.72 0.82 0.98 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.12/ ?0.05 0.14/ ?0.05 0.17/ ?0.05 ns sequential delays t oscko_oq clock to out from clk to oq 0.28 0.32 0.37 ns t oscko_tq clock to out from clk to tq 0.28 0.32 0.37 ns combinatorial t osdo_ttq t input to tq out 0.78 0.88 1.03 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in trace report.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 30 input/output delay swit ching characteristics ta bl e 3 4 : input/output delay switching characteristics symbol description speed grade units -3 -2 -1 -1l idelayctrl t dlycco_rdy reset to ready for idelayctrl 3.25 3.25 3.25 s f idelayctrl_ref attribute refclk frequency = 200.0 (1) 200 200 200 mhz attribute refclk frequency = 300.0 (1) 300 300 n/a mhz idelayctrl_ref_precision refclk precision 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 52.5 52.5 52.5 ns idelay/odelay t idelayresolution idelay/odelay chain delay resolution 1/(32 x 2 x f ref )ps t idelaypat_jit_clock pattern dependent period jitter in delay chain for clock pattern. (hp i/o banks only) (2) 000 ps per tap t idelaypat_jit_data pattern dependent period jitter in delay chain for random data pattern (prbs 23) (hp i/o banks only) (2) 5 5 5 ps per tap t idelaypat_jit_clock pattern dependent period jitter in delay chain for clock pattern. (hr i/o banks only) (2) 000 ps per tap t idelaypat_jit_data pattern dependent period jitter in delay chain for random data pattern (prbs 23) (hr i/o banks only) (2) 9 9 9 ps per tap t idelay_clk_max / t odelay_clk_max maximum frequency of clk input to idelay/odelay 800 800 710 mhz t idcck_ce / t idckc_ce ce pin setup/hold with respect to c for idelay ?0.02/ 0.21 ?0.02/ 0.24 ?0.02/ 0.30 ns t odcck_ce / t odckc_ce ce pin setup/hold with respect to c for odelay ?0.02/ 0.21 ?0.02/ 0.25 ?0.02/ 0.30 ns t idcck_inc / t idckc_inc inc pin setup/hold with respect to c for idelay 0.10/ 0.24 0.11/ 0.28 0.12/ 0.34 ns t odcck_inc / t odckc_inc inc pin setup/hold with respect to c for odelay 0.11/ 0.24 0.11/ 0.28 0.12/ 0.34 ns t idcck_rst / t idckc_rst rst pin setup/hold with respect to c for idelay 0.10/ 0.26 0.12/ 0.31 0.14/ 0.38 ns t odcck_rst / t odckc_rst rst pin setup/hold with respect to c for odelay 0.10/ 0.27 0.12/ 0.32 0.15/ 0.38 ns t iddo_idatain propagation delay through idelay note 2 note 2 note 2 ps t oddo_odatain propagation delay through odelay note 2 note 2 note 2 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps. 2. delay depends on idelay/odelay tap setting. see trace report for actual values.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 31 clb switching characteristics ta bl e 3 5 : clb switching characteristics symbol description speed grade units -3 -2 -1 -1l combinatorial delays t ilo an ? dn lut address to a 0.04 0.05 0.07 ns, max t ilo_2 an ? dn lut address to amux/cmux 0.16 0.18 0.22 ns, max t ilo_3 an ? dn lut address to bmux_a 0.26 0.30 0.35 ns, max t ito an ? dn inputs to a ? d q outputs 0.64 0.74 0.87 ns, max t axa ax inputs to amux output 0.34 0.40 0.48 ns, max t axb ax inputs to bmux output 0.35 0.42 0.50 ns, max t axc ax inputs to cmux output 0.39 0.44 0.52 ns, max t axd ax inputs to dmux output 0.43 0.48 0.56 ns, max t bxb bx inputs to bmux output 0.29 0.36 0.44 ns, max t bxd bx inputs to dmux output 0.34 0.41 0.49 ns, max t cxc cx inputs to cmux output 0.25 0.29 0.34 ns, max t cxd cx inputs to dmux output 0.30 0.35 0.40 ns, max t dxd dx inputs to dmux output 0.32 0.36 0.40 ns, max t opcya an input to cout out put 0.29 0.35 0.41 ns, max t opcyb bn input to cout out put 0.29 0.35 0.42 ns, max t opcyc cn input to cout output 0.23 0.26 0.30 ns, max t opcyd dn input to cout output 0.22 0.26 0.30 ns, max t axcy ax input to cout output 0.26 0.30 0.34 ns, max t bxcy bx input to cout output 0.20 0.23 0.26 ns, max t cxcy cx input to cout outp ut 0.15 0.17 0.19 ns, max t dxcy dx input to cout outp ut 0.14 0.16 0.19 ns, max t byp cin input to cout output 0.06 0.06 0.07 ns, max t cina cin input to amux output 0.22 0.26 0.31 ns, max t cinb cin input to bmux output 0.24 0.28 0.33 ns, max t cinc cin input to cmux output 0.22 0.25 0.30 ns, max t cind cin input to dmux output 0.26 0.29 0.34 ns, max sequential delays t cko clock to aq ? dq outputs 0.26 0.30 0.35 ns, max t shcko clock to amux ? dmux outputs 0.32 0.36 0.43 ns, max setup and hold times of clb fl ip-flops before/after clock clk t dick /t ckdi a ? d input to clk on a ? d flip flops 0.33/ 0.14 0.38/ 0.17 0.44/ 0.20 ns, min t ceck_clb / t ckce_clb ce input to clk on a ? d flip flops 0.21/ 0.01 0.27/ 0.01 0.35/ 0.01 ns, min t srck /t cksr sr input to clk on a ? d flip flops 0.41/ ?0.06 0.46/ ?0.06 0.55/ ?0.06 ns, min t cinck /t ckcin cin input to clk on a ? d flip flops 0.15/ 0.12 0.17/ 0.14 0.20/ 0.16 ns, min
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 32 clb distributed ram switching characteristics (slicem only) set/reset t srmin sr input minimum pulse width 0.50 0.75 1.00 ns, min t rq delay from sr input to aq ? dq flip-flops 0.55 0.61 0.71 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.44 0.51 0.61 ns, max f tog toggle frequency (for export control) 1412 1286 1098 mhz notes: 1. a zero ?0? hold time listing indicates no hold ti me or a negative hold time. negative values can not be guaranteed ?best-case?, but if a ?0? is listed, there is no positive hold time. 2. these items are of interest for carry chain applications. ta bl e 3 6 : clb distributed ram swit ching characteristics symbol description speed grade units -3 -2 -1 -1l sequential delays t shcko clock to a ? b outputs 0.99 1.18 1.46 ns, max t shcko_1 clock to amux ? bmux outputs 1.26 1.48 1.80 ns, max setup and hold times before/after clock clk t ds_lram /t dh_lram a ? d inputs to clk 0.64/ 0.21 0.75/ 0.23 0.91/ 0.26 ns, min t as_lram /t ah_lram address an inputs to clock 0.17/ 0.46 0.21/ 0.50 0.26/ 0.58 ns, min t ws_lram /t wh_lram we input to clock 0.27/ 0.03 0.33/ 0.03 0.41/ 0.03 ns, min t ceck_lram / t ckce_lram ce input to clk 0.28/ 0.02 0.34/ 0.02 0.42/ 0.02 ns, min clock clk t mpw_lram minimum pulse width 0.77 0.90 1.09 ns, min t mcp minimum clock period 1.53 1.79 2.18 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. 2. t shcko also represents the clk to xmux output. refer to trace report for the clk to xmux path. ta bl e 3 5 : clb switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 33 clb shift register switching characteristics (slicem only) block ram and fifo switching characteristics ta bl e 3 7 : clb shift register switching characteristics symbol description speed grade units -3 -2 -1 -1l sequential delays t reg clock to a ? d outputs 1.18 1.39 1.69 ns, max t reg_mux clock to amux ? dmux output 1.45 1.68 2.04 ns, max t reg_m31 clock to dmux output via m 31 output 1.16 1.36 1.66 ns, max setup and hold times before/after clock clk t ws_shfreg / t wh_shfreg we input 0.04/ 0.03 0.06/ 0.03 0.08/ 0.03 ns, min t ceck_shfreg / t ckce_shfreg ce input to clk 0.05/ 0.02 0.07/ 0.02 0.09/ 0.02 ns, min t ds_shfreg / t dh_shfreg a ? d inputs to clk 0.66/ 0.21 0.78/ 0.24 0.97/ 0.28 ns, min clock clk t mpw_shfreg minimum pulse width 0.66 0.77 0.93 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. ta bl e 3 8 : block ram and fifo switching characteristics symbol description speed grade units -3 -2 -1 -1l block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg (1) clock clk to dout out put (without output register) (2)(3) 1.83 2.03 2.34 ns, max clock clk to dout output (with output register) (4)(5) 0.56 0.62 0.71 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without outpu t register) (2)(3) 2.38 2.74 3.27 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.58 0.65 0.76 ns, max t rcko_do_cascout and t rcko_do_cascout_reg clock clk to dout output with cascade (without outpu t register) (2) 2.18 2.46 2.88 ns, max clock clk to dout output with cascade (with output register) (4) 1.01 1.12 1.29 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.69 0.75 0.84 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 0.79 0.86 0.97 ns, max t rcko_parity_ecc clock clk to eccparity in ecc encode only mode 0.66 0.72 0.81 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (without output register) 2.20 2.53 3.03 ns, max clock clk to biterr (with output register) 0.54 0.60 0.70 ns, max
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 34 t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without outpu t register) 0.64 0.70 0.80 ns, max clock clk to rdaddr output with ecc (with output register) 0.69 0.77 0.88 ns, max setup and hold times before/after clock clk t rcck_addra /t rckc_addra addr inputs (8) 0.37/ 0.21 0.40/ 0.23 0.45/ 0.25 ns, min t rdck_di /t rckd_di din inputs (9) 0.87/ 0.22 0.99/ 0.23 1.18/ 0.24 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.35/ 0.22 0.41/ 0.23 0.52/ 0.24 ns, min din inputs with block ram ecc encode only (9) 0.76/ 0.22 0.88/ 0.23 1.05/ 0.24 ns, min din inputs with fifo ecc in standard mode (9) 0.87/ 0.22 0.99/ 0.23 1.18/ 0.24 ns, min t rcck_clk /t rckc_clk inject single/double bit error in ecc mode 0.51/ 0.17 0.58/ 0.18 0.68/ 0.18 ns, min t rcck_rden /t rckc_rden block ram enable (en) input 0.36/ 0.18 0.39/ 0.19 0.44/ 0.21 ns, min t rcck_regce /t rckc_regce ce input of out put register 0.32/ 0.05 0.34/ 0.06 0.39/ 0.06 ns, min t rcck_rstreg /t rckc_rstreg synchronous rstreg input (10) 0.37/ 0.04 0.40/ 0.04 0.45/ 0.04 ns, min t rcck_rstram /t rckc_rstram synchronous rstram input 0.24/ 0.14 0.25/ 0.15 0.27/ 0.16 ns, min t rcck_wea /t rckc_wea write enable (we) input (block ram only) 0.39/ 0.15 0.43/ 0.16 0.49/ 0.17 ns, min t rcck_wren /t rckc_wren wren fifo inputs 0.46/ 0.18 0.51/ 0.19 0.59/ 0.21 ns, min t rcck_rden /t rckc_rden rden fifo inputs 0.42/ 0.18 0.49/ 0.19 0.59/ 0.21 ns, min reset delays (flags) t rco_rst reset rst to fifo flags/pointers (11) 0.76 0.83 0.94 ns, max maximum frequency f max_bram_wf_nc block ram (write first and no change modes) when not in sdp rf mode 601 544 458 mhz f max_bram_rf_performance block ram (read first, performance mode) when in sdp rf mode but no address overlap between port a and port b 601 544 458 mhz f max_bram_rf_delayed_write block ram (read first, delayed_write mode) when in sdp rf mode and there is possibility of overlap between port a and port b addresses 541 485 401 mhz ta bl e 3 8 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 35 f max_cas_wf_nc block ram cascade (write first, no change mode) when cascade but not in rf mode 529 475 392 mhz f max_cas_rf_performance block ram cascade (read first, performance mode) when in cascade with rf mode and no possibility of address overlap/one port is disabled 529 475 392 mhz f max_cas_rf_delayed_write when in cascade rf mode and there is a possibility of address overlap between port a and port b 492 437 353 mhz f max_fifo fifo in all modes without ecc 601 544 458 mhz f max_ecc block ram and fifo in ecc configuration 495 427 326 mhz notes: 1. trace will report all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted) . otherwise, block ram data corruption is possible. 9. t rcko_di includes both a and b inputs as well as the parity inputs of a and b. 10. rden and wren must be held low prior to and during reset. the fifo reset must be asserted for at least five positive clock e dges of the slowest clock (wrclk or rdclk). 11. t rco_flags includes the following flags: aempty, afull, em pty, full, rderr, wrerr, rdcount, and wrcount. ta bl e 3 8 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 36 dsp48e1 switching characteristics ta bl e 3 9 : dsp48e1 switching characteristics symbol description speed units -3 -2 -1 -1l setup and hold times of data/control pins to the input register clock t dspdck_a_areg / t dspckd_a_areg a input to a register clk 0.31/ 0.10 0.37/ 0.11 0.51/ 0.16 ns t dspdck_b_breg /t dspckd_b_breg b input to b register clk 0.36/ 0.11 0.42/ 0.12 0.57/ 0.17 ns t dspdck_c_creg /t dspckd_c_creg c input to c register clk 0.24/ 0.15 0.28/ 0.16 0.40/ 0.22 ns t dspdck_d_dreg /t dspckd_d_dreg d input to d register clk 0.29/ 0.14 0.35/ 0.15 0.50/ 0.20 ns t dspdck_acin_areg /t dspckd_acin_areg acin input to a register clk 0.28/ 0.10 0.34/ 0.11 0.47/ 0.16 ns t dspdck_bcin_breg /t dspckd_bcin_breg bcin input to b register clk 0.30/ 0.11 0.35/ 0.12 0.48/ 0.17 ns setup and hold times of data pins to the pipeline register clock t dspdck_ { a, b } _mreg_mult / t dspckd_b_mreg_mult {a, b,} input to m register clk using multiplier 2.43/ ?0.03 2.81/ ?0.03 3.61/ 0.01 ns t dspdck_ { a, b } _adreg / t dspckd_ d_adreg {a, d} input to ad register clk 1.28/ ?0.04 1.46/ ?0.04 1.85/ ?0.03 ns setup and hold times of data/control pins to the output register clock t dspdck_{ a, b }_preg_mult / t dspckd_{ a, b } _preg_mult {a, b,} input to p register clk using multiplier 3.97/ ?0.16 4.57/ ?0.16 5.78/ ?0.16 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk using multiplier 3.87/ ?0.56 4.48/ ?0.56 5.69/ ?0.56 ns t dspdck_b_preg / t dspckd_b_preg b input to p register clk not using multiplier 1.70/ ?0.16 1.94/ ?0.16 2.45/ ?0.16 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk not using multiplier 1.50/ ?0.13 1.72/ ?0.13 2.18/ ?0.13 ns t dspdck_pcin_preg / t dspckd_pcin_preg pcin input to p register clk 1.30/ ?0.04 1.48/ ?0.04 1.87/ ?0.03 ns setup and hold times of the ce pins t dspdck_{cea;ceb}_{areg;breg} / t dspckd_{cea;ceb}_{areg;breg} {cea; ceb} input to {a; b} register clk 0.38/ 0.08 0.46/ 0.09 0.62/ 0.13 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk 0.31/ 0.09 0.38/ 0.10 0.51/ 0.14 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk 0.40/ ?0.03 0.47/ ?0.03 0.63/ ?0.02 ns t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk 0.31/ 0.06 0.37/ 0.07 0.51/ 0.10 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.36/ 0.02 0.43/ 0.02 0.58/ 0.05 ns setup and hold times of the rst pins t dspdck_{rsta; rstb}_{areg; breg} / t dspckd_{rsta; rstb}_{areg; breg} {rsta, rstb} input to {a, b} register clk 0.42/ 0.11 0.49/ 0.12 0.63/ 0.16 ns t dspdck_rstc_creg / t dspckd_rstc_creg rstc input to c register clk 0.10/ 0.08 0.12/ 0.09 0.17/ 0.13 ns
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 37 t dspdck_rstd_dreg / t dspckd_rstd_dreg rstd input to d register clk 0.47/ 0.07 0.55/ 0.08 0.71/ 0.12 ns t dspdck_rstm_mreg / t dspckd_rstm_mreg rstm input to m register clk 0.37/ 0.08 0.43/ 0.09 0.55/ 0.12 ns t dspdck_rstp_preg / t dspckd_rstp_preg rstp input to p register clk 0.26/ 0.02 0.30/ 0.03 0.39/ 0.05 ns combinatorial delays from input pins to output pins t dspdo_a_carryout_mult a input to carryout output using multiplier 3.75 4.32 5.46 ns t dspdo_d_p_mult d input to p output using multiplier 3.67 4.25 5.40 ns t dspdo_b_p b input to p output not usin g multiplier 1.50 1.72 2.16 ns t dspdo_c_p c input to p output 1.30 1.50 1.89 ns combinatorial delays from input pins to cascading output pins t dspdo_{a; b}_{acout; bcout} {a, b} input to {acout, bcout} output 0.54 0.62 0.79 ns t dspdo_{a, b}_carrycascout_mult {a, b} input to carrycascout output using multiplier 3.99 4.60 5.81 ns t dspdo_d_carrycascout_mult d input to carrycascout output using multiplier 3.90 4.51 5.72 ns t dspdo_{a, b}_carrycascout {a, b} input to carrycascout output not using multiplier 1.72 1.98 2.48 ns t dspdo_c_carrycascout c input to carrycascout output 1.52 1.75 2.21 ns combinatorial delays from cascading input pins to all output pins t dspdo_acin_p_mult acin input to p output using multiplier 3.58 4.13 5.23 ns t dspdo_acin_p acin input to p output not using multiplier 1.31 1.51 1.91 ns t dspdo_acin_acout acin input to acout output 0.35 0.41 0.53 ns t dspdo_acin_carrycascout_mult acin input to carrycascout output using multiplier 3.81 4.39 5.55 ns t dspdo_acin_carrycascout acin input to carrycascout output not using multiplier 1.54 1.77 2.23 ns t dspdo_pcin_p pcin input to p output 1.10 1.26 1.57 ns t dspdo_pcin_c arrycascout pcin input to carrycas cout output 1.32 1.51 1.90 ns clock to outs from output re gister clock to output pins t dspcko_p_preg clk (preg) to p output 0.29 0.33 0.42 ns t dspcko_carrycascout_preg clk (preg) to carrycascout output 0.48 0.54 0.68 ns clock to outs from pipeline register clock to output pins t dspcko_p_mreg clk (mreg) to p output 1.58 1.82 2.30 ns t dspcko_carrycascout_mreg clk (mreg) to carrycascout output 1.80 2.07 2.62 ns t dspcko_p_adreg_mult clk (adreg) to p output using multiplier 2.68 3.09 3.91 ns t dspcko_carrycascout_adreg_mult clk (adreg) to carrycascout output using multiplier 2.91 3.35 4.23 ns ta bl e 3 9 : dsp48e1 switching characteristics (cont?d) symbol description speed units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 38 clock to outs from input re gister clock to output pins t dspcko_p_areg_mult clk (areg) to p output using multiplier 3.87 4.46 5.63 ns t dspcko_p_breg clk (breg) to p output not using multiplier 1.58 1.81 2.26 ns t dspcko_p_creg clk (creg) to p output not using multiplier 1.62 1.85 2.32 ns t dspcko_p_dreg_mult clk (dreg) to p output using multiplier 3.84 4.45 5.64 ns clock to outs from input register clock to cascadi ng output pins t dspcko_{acout; bcout}_{areg; breg} clk (acout, bcout) to {a,b} register output 0.61 0.70 0.89 ns t dspcko_carrycascout_{areg, breg}_mult clk (areg, breg) to carrycascout output using multiplier 4.10 4.72 5.95 ns t dspcko_carrycascout_ breg clk (breg) to carrycascout output not using multiplier 1.80 2.06 2.59 ns t dspcko_carrycascout_ dreg_mult clk (dreg) to carrycascout output using multiplier 4.07 4.70 5.97 ns t dspcko_carrycascout_ creg clk (creg) to carrycascout output 1.84 2.11 2.64 ns maximum frequency f max with all registers used 617 533 419 mhz f max_patdet with pattern detector 533 461 363 mhz f max_mult_nomreg two register multiply without mreg 350 304 241 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 321 279 221 mhz f max_preadd_mult_noadreg without adreg 399 345 272 mhz f max_preadd_mult_noadreg_patdet without adreg with pattern detect 399 345 272 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 263 228 181 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 246 214 169 mhz ta bl e 3 9 : dsp48e1 switching characteristics (cont?d) symbol description speed units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 39 configuration switching characteristics ta bl e 4 0 : configuration switching characteristics symbol description speed grade units -3 -2 -1 -1l power-up timing characteristics t pl (1) program latency ms, max t por (1) power-on-reset 50 ms, max t icck cclk (output) delay ns, min t program program pulse width 250 ns, min master/slave serial mode programming switching t dcck /t cckd din setup/hold, slave mode 5.0/0.0 ns, min t dscck /t scckd din setup/hold, master mode 5.0/0.0 ns, min t cco dout at 3.3v ns, max dout at 2.5v ns, max dout at 1.8v ns, max f mcck maximum frequency, master mode with respect to nominal cclk. 100 mhz, max f mccktol frequency tolerance, master mode with respect to nominal cclk. 55 % f mscck slave mode external cclk 100 mhz selectmap mode programming switching t smdcck /t smcckd selectmap data setup/hold 5.0/0.0 ns, min t smcscck /t smcckcs csi_b setup/hold ns, min t smcckw /t smwcck rdwr_b setup/hold ns, min t smckcso cso_b clock to out (330 ? pull-up resistor required) ns, max t smco cclk to data out in readback at 3.3v ns, max cclk to data out in readback at 2.5v ns, max cclk to data out in readback at 1.8v ns, max f smcck maximum frequency with respect to nominal cclk. 100 mhz, max f rbcck maximum readback frequency with respect to nominal cclk 70 mhz, max f mccktol frequency tolerance with respect to nominal cclk. 55 % boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup time befo re tck/ hold time after tck ns, min t tcktdo tck falling edge to tdo output valid at 3.3v ns, max tck falling edge to tdo output valid at 2.5v ns, max tck falling edge to tdo output valid at 1.8v ns, max f tck maximum configuration tck clock frequency 20 mhz, max f tckb maximum boundary-scan tck clock frequency 20 mhz, max
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 40 bpi master flash mode programming switching t bpicco (2) a[28:00], rs[1:0], fcs_b, foe_b, fwe_b, adv_b outputs valid after cclk rising edge at 3.3v ns a[28:00], rs[1:0], fcs_b, foe_b, fwe_b, adv_b outputs valid after cclk rising edge at 2.5v ns a[28:00], rs[1:0], fcs_b, foe_b, fwe_b, adv_b outputs valid after cclk rising edge at 1.8v ns t bpidcc /t bpiccd setup/hold on d[15:00] data input pins 5.0/0.0 ns spi master flash mode programming switching t spidcc /t spidccd din setup/hold before/after the rising cclk edge 5.0/0.0 ns t spiccm mosi clock to out at 3.3v ns mosi clock to out at 2.5v ns mosi clock to out at 1.8v ns t spiccfc fcs_b clock to out at 3.3v ns fcs_b clock to out at 2.5v ns fcs_b clock to out at 1.8v ns cclk output (master modes) f mcck_start master cclk frequency at start of configuration 2 mhz, typ t mcckl master cclk clock low ti me duty cycle %, min/max t mcckh master cclk clock high ti me duty cycle %, min/max cclk input (slave modes) t scckl slave cclk clock minimum low time ns, min t scckh slave cclk clock minimum high time ns, min dynamic reconfiguration port (drp) for mmcm before and after dclk f dck maximum frequency for dclk 200 200 200 mhz t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 ns t mmcmdck_di / t mmcmckd_di di setup/hold 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 ns t mmcmdck_den / t mmcmckd_den den setup/hold time 1.76/ 0.00 1.97/ 0.00 2.29/ 0.00 ns t mmcmdck_dwe / t mmcmckd_dwe dwe setup/hold time 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 ns t mmcmcko_do clk to out of do (3) 3.05 3.54 4.27 ns t mmcmcko_drdy clk to out of drdy 0.37 0.40 0.44 ns notes: 1. to support longer delays in configuration, use the design solutions described in 7 series fpga configuration user guide . 2. only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the i/o. 3. do will hold until next drp operation. ta bl e 4 0 : configuration switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 41 clock buffers and networks ta bl e 4 1 : global clock switching characte ristics (incl uding bufgctrl) symbol description speed grade units -3 -2 -1 -1l t bccck_ce /t bcckc_ce (1) ce pins setup/hold 0.10/ 0.04 0.12/ 0.05 0.15/ 0.05 ns t bccck_s /t bcckc_s (1) s pins setup/hold 0.10/ 0.04 0.12/ 0.05 0.15/ 0.05 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.08 0.09 0.11 ns maximum frequency f max_bufg global clock tree (bufg) 710 710 625 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux primitive that assures glitch-free operation. the other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switchin g between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. ta bl e 4 2 : input/output clock switching characteristics (bufio) symbol description speed grade units -3 -2 -1 -1l t biocko_o clock to out delay from i to o 1.14 1.29 1.52 ns maximum frequency f max_bufio i/o clock tree (bufio) 800 800 650 mhz ta bl e 4 3 : regional clock buffer switching characteristics (bufr) symbol description speed grade units -3 -2 -1 -1l t brcko_o clock to out delay from i to o 0.77 0.87 1.03 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.39 0.44 0.53 ns t brdo_o propagation delay from clr to o 0.67 0.76 0.89 ns maximum frequency f max_bufr (1) regional clock tree (bufr) 575 484 345 mhz notes: 1. the maximum input frequency to the bufr is the bufio f max frequency. ta bl e 4 4 : horizontal clock buffer switching characteristics (bufh) symbol description speed grade units -3 -2 -1 -1l t bhcko_o bufh delay from i to o 0.07 0.09 0.11 ns t bhcck_ce /t bhckc_ce ce pin setup and hold 0.09/ 0.05 0.11/ 0.05 0.14/ 0.06 ns maximum frequency f max_bufh horizontal clock buffer (bufh) 710 710 625 mhz
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 42 mmcm switching characteristics ta bl e 4 5 : mmcm specification symbol description speed grade units -3 -2 -1 -1l mmcm_f inmax maximum input clock frequency 1066 933 800 mhz mmcm_f inmin minimum input clock frequency 10 10 10 mhz f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max mmcm_f induty allowable input duty cycle: 10?49 mhz 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 % mmcm_f min_psclk minimum dynamic phase shift clock frequency 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase shift clock frequency 550 500 450 mhz mmcm_f vcomin minimum mmcm vco frequency 600 600 600 mhz mmcm_f vcomax maximum mmcm vco frequency 1600 1440 1200 mhz mmcm_f bandwidth low mmcm bandwidth at typical (1) 1.22 1.22 1.22 mhz high mmcm bandwidth at typical (1) 4.88 4.88 4.88 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs (2) 0.12 0.12 0.12 ns t outjitter pll output jitter (3) note 1 mmcm_t outduty mmcm output clock duty cycle precision (4) 0.19 0.25 0.25 ns mmcm_t lockmax mmcm maximum lock time 122 122 122 s mmcm_f outmax mmcm maximum output frequency 1066 933 800 mhz mmcm_f outmin mmcm minimum output frequency (5)(6) 4.69 4.69 4.69 mhz t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max mmcm_rst minpulse minimum reset pulse width 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector with bandwidth se t to high or optimized 550 500 450 mhz maximum frequency at the phase frequency detector with bandwidth set to low 550 500 450 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector 10 10 10 mhz mmcm switching characteristics setup and hold t mmcmdck_psen / t mmcmckd_psen setup and hold of phase shift enable 1.04/ 0.00 1.04/ 0.00 1.04/ 0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase shift increment/decrement 1.04/ 0.00 1.04/ 0.00 1.04/ 0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone 0.37 0.40 0.44 ns notes: 1. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are available in the architecture wizard. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when cascade4_out = true, f outmin is 0.036 mhz.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 43 pll switching characteristics ta bl e 4 6 : pll specification symbol description speed grade units -3 -2 -1 -1l f inmax maximum input clock frequency 1066 933 800 mhz f inmin minimum input clock frequency 19 19 19 mhz f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max f induty allowable input duty cycle: 19?49 mhz 25 25 25 % allowable input duty cycle: 50?199 mhz 30 30 30 % allowable input duty cycle: 200?399 mhz 35 35 35 % allowable input duty cycle: 400?499 mhz 40 40 40 % allowable input duty cycle: >500 mhz 45 45 45 % f vcomin minimum pll vco frequency 800 800 800 mhz f vcomax maximum pll vco frequency 2133 1866 1600 mhz f bandwidth low pll bandwidth at typical (1) 1.00 1.00 1.00 mhz high pll bandwidth at typical (1) 4.00 4.00 4.00 mhz t statphaoffset static phase offset of the pll outputs (2) 0.12 0.12 0.12 ns t outjitter pll output jitter (3) note 1 t outduty pll output clock duty cycle precision (4) 0.15 0.20 0.20 ns t lockmax pll maximum lock time 100 100 100 s f outmax pll maximum output frequency 1066 933 800 mhz f outmin pll minimum output frequency (5)(6) 6.25 6.25 6.25 mhz t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max rst minpulse minimum reset pulse width 5.00 5.00 5.00 ns f pfdmax maximum frequency at the phase frequency detector with bandwidth se t to high or optimized 550 500 450 mhz maximum frequency at the phase frequency detector with bandwidth set to low 550 500 450 mhz f pfdmin minimum frequency at the phase frequency detector 19 19 19 mhz t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 44 pll switching characteristics setup and hold t pllcck_den / t pllckc_den setup and hold of d enable 1.76/ 0.00 1.97/ 0.00 2.29/ 0.00 ns t pllcck_daddr / t pllckc_daddr setup and hold of d address 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 ns t pllcck_di / t pllckc_di setup and hold of d input 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 ns t pllcck_dwe / t pllckc_dwe setup and hold of d write enable 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 ns notes: 1. the pll does not filter typical spread-spectrum input cloc ks because they are usually far below the bandwidth filter frequenc ies. 2. the static offset is measured between any pll outputs with identical phase. 3. values for this parameter are available in the architecture wizard. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when cascade4_out = true, f outmin is 0.036 mhz. ta bl e 4 6 : pll specification (cont?d) symbol description speed grade units -3 -2 -1 -1l
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 45 kintex-7 device pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 4 7 . values are expressed in nanoseconds unless otherwise noted. ta bl e 4 7 : clock-capable clock input to output delay without mmcm/pll (near clock region) symbol description device speed grade units -3 -2 -1 -1l lvcmos clock-capable clock input to output delay using output flip-flop, 12ma, fast slew rate, without mmcm/pll. t ickof clock-capable clock input and outff without mmcm/pll (near clock region) xc7k70t 6.36 7.02 8.04 ns xc7k160t 6.18 6.83 7.82 ns xc7k325t 7.03 7.77 8.89 ns xc7k355t ns xc7k410t 7.16 7.90 9.04 ns xc7k420t ns xc7k480t ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. ta bl e 4 8 : clock-capable clock input to output delay without mmcm/pll (far clock region) symbol description device speed grade units -3 -2 -1 -1l lvcmos clock-capable clock input to output delay using output flip-flop, 12ma, fast slew rate, without mmcm/pll. t ickof_far clock-capable clock input and outff without mmcm/pll (far clock region) xc7k70t 6.61 7.30 8.35 ns xc7k160t 6.70 7.39 8.45 ns xc7k325t 7.55 8.33 9.52 ns xc7k355t ns xc7k410t 7.67 8.46 9.67 ns xc7k420t ns xc7k480t ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 46 ta bl e 4 9 : clock-capable clock input to output delay with mmcm symbol description device speed grade units -3 -2 -1 -1l lvcmos clock-capable clock input to output delay using output flip-flop, 12ma, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc7k70t 2.37 2.45 2.52 ns xc7k160t 2.38 2.47 2.55 ns xc7k325t 2.33 2.41 2.48 ns xc7k355t ns xc7k410t 2.35 2.43 2.50 ns xc7k420t ns xc7k480t ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. ta bl e 5 0 : clock-capable clock input to output delay with pll symbol description device speed grade units -3 -2 -1 -1l lvcmos clock-capable clock input to output delay using output flip-flop, 12ma, fast slew rate, with pll. t ickof_pll_cc clock-capable clock input and outff with pll xc7k70t 2.37 2.45 2.52 ns xc7k160t 2.35 2.43 2.50 ns xc7k325t 2.33 2.41 2.48 ns xc7k355t ns xc7k410t 2.35 2.43 2.50 ns xc7k420t ns xc7k480t ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is already included in the timing calculation.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 47 kintex-7 device pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 5 1 . values are expressed in nanoseconds unless otherwise noted. ta bl e 5 1 : global clock input setup and hold without mmcm/pll with zhold_delay on hr i/o banks symbol description device speed grade units -3 -2 -1 -1l input setup and hold time relative to global clock input signal for lvcmos standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm/pll with zhold_delay on hr i/o banks xc7k70t ?0.41/ 2.29 ?0.41/ 2.57 ?0.41/ 3.01 ns xc7k160t ?0.23/ 2.11 ?0.23/ 2.37 ?0.23/ 2.78 ns xc7k325t ?0.49/ 2.70 ?0.49/ 3.02 ?0.49/ 3.53 ns xc7k355t ns xc7k410t ?0.58/ 2.83 ?0.58/ 3.17 ?0.58/ 3.69 ns xc7k420t ns xc7k480t ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. ta bl e 5 2 : clock-capable clock input setup and hold with mmcm symbol description device speed grade units -3 -2 -1 -1l input setup and hold time relative to global clock input signal for lvcmos standard. (1) t psmmcmcc / t phmmcmcc no delay clock-capable clock input and iff (2) with mmcm xc7k70t 1.75/ ?0.50 1.94/ ?0.50 2.22/ ?0.50 ns xc7k160t 1.80/ ?0.49 1.99/ ?0.49 2.27/ ?0.49 ns xc7k325t 1.89/ ?0.53 2.11/ ?0.53 2.43/ ?0.53 ns xc7k355t ns xc7k410t 1.89/ ?0.53 2.11/ ?0.53 2.43/ ?0.53 ns xc7k420t ns xc7k480t ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 48 clock switching characteristics the parameters in this section provide the necessary valu es for calculating timing budgets for kintex-7 fpga clock transmitter and receiver data-valid windows. ta bl e 5 3 : clock-capable clock input setup and hold with pll symbol description device speed grade units -3 -2 -1 -1l input setup and hold time relative to clock-capable clock input signal for lvcmos standard. (1) t pspllcc / t phpllcc no delay clock-capable clock input and iff (2) with pll xc7k70t 1.75/ ?0.50 1.94/ ?0.50 2.22/ ?0.50 ns xc7k160t 1.80 ?0.49 1.99 ?0.49 2.27 ?0.49 ns xc7k325t 1.89 ?0.53 2.11 ?0.53 2.43 ?0.53 ns xc7k355t ns xc7k410t 1.89 ?0.53 2.11 ?0.53 2.43 ?0.53 ns xc7k420t ns xc7k480t ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 5 4 : duty cycle distortion and clock-tree skew symbol description device speed grade units -3 -2 -1 -1l t dcd_clk global clock tree duty cycle distortion (1) all 0.12 0.12 0.12 ns t ckskew global clock tree skew (2) xc7k70t 0.18 0.20 0.22 ns xc7k160t 0.32 0.36 0.40 ns xc7k325t 0.47 0.52 0.59 ns xc7k355t ns xc7k410t 0.47 0.52 0.59 ns xc7k420t ns xc7k480t ns t dcd_bufio i/o clock tree duty cycle distortion all 0.08 0.08 0.08 ns t bufioskew i/o clock tree skew across one clock region all 0.04 0.04 0.03 ns t dcd_bufr regional clock tree duty cycle distortion all 0.15 0.15 0.15 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to your application.
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 49 ta bl e 5 5 : package skew symbol description device package value units t pkgskew package skew (1) xc7k70t fbg484 ps fbg676 ps xc7k160t fbg484 ps fbg676 ps ffg676 ps xc7k325t fbg676 ps ffg676 ps fbg900 ps ffg900 ps xc7k355t ffg901 ps xc7k410t fbg676 ps ffg676 ps fbg900 ps ffg900 ps xc7k420t ffg901 ps ffg1156 ps xc7k480t ffg901 ps ffg1156 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest flight time to longest flight time from pad to ball (7.0 ps per mm). 2. package trace length information is available for these device/package combinations. this information can be used to deskew t he package. ta bl e 5 6 : sample window symbol description speed grade units -3 -2 -1 -1l t samp sampling error at receiver pins (1) 0.51 0.56 0.61 ps t samp_bufio sampling error at receiver pins using bufio (2) 0.30 0.35 0.40 ps notes: 1. this parameter indicates the total sampling error of the kintex-7 fpgas ddr input registers, measured across voltage, tempera ture, and process. the characterization methodology uses the mmcm to capture the ddr input registers? edges of operation. these measureme nts include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of the kintex-7 fpgas ddr input registers, measured across voltage, tempera ture, and process. the characterization methodology uses the bufio clock network and idelay to capture the ddr input registers? edges of operation. these measurements do not include package or clock tree skew. ta bl e 5 7 : pin-to-pin setup/hold and clock-to-out symbol description speed grade units -3 -2 -1 -1l data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock ?0.20/ 1.79 ?0.20/ 2.01 ?0.20/ 2.33 ns pin-to-pin clock-to -out using bufio t ickofcs clock-to-out of i/o clock 6.29 6.98 8.02 ns
kintex-7 fpgas data sheet: dc and switching characteristics ds182 (v1.1) april 1, 2011 www.xilinx.com advance product specification 50 revision history the following table shows the revision history for this document: notice of disclaimer the information disclosed to you hereunder (the "materials") is provided solely for the selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are m ade available "as is" and with all faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or stat utory, including but not limited to warranties of merchantability, non-infringement, or fitness for any pa rticular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under an y other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includi ng your use of the materials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of da ta, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had been advised of the p ossibility of the same. xilinx assumes no obligation to correct any errors contained in the materials, or to advise you of any corrections or update. you may not reproduce, modify, distribute, or publicly display the materials without prior writt en consent. certain products ar e subject to the terms and conditions of the limited warranties which can be viewed at http://www.xilinx.com/warranty.htm ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be f ail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of xilinx products in cr itical applications: http://www.xilinx.com/warranty.htm#critapps . automotive applications disclaimer xilinx products are not designed or intended to be fail -safe, or for use in any application requiring fail- safe performance, such as applications related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. customer assumes the sole risk and liability of any use of xilinx products in such applications. date version description 03/01/11 1.0 initial xilinx release. 04/01/11 1.1 added the xc7k355t, xc7k420t, and xc7k480t devices throughout data sheet. added the extended temperature range discussion to page 1 . updated v ccaux_io in ta bl e 2 . edits to clarify power-on/off power supply requirements power sequencing discussion. added i ccaux_io and i ccbram to ta b l e 4 and ta b l e 5 . updated mmcm_f induty and added f injitter , t outjitter , t extfdvar , and note 3 to ta bl e 4 5 . removed the sbg324 package from ta b l e 5 5 . updated the notice of disclaimer .

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